Okay... Part Two.
(In which our hero loses his way, and settles down with a sandwich.)
So.... we've looked at the first ladder and how it affects the signal level being fed INTO the detector stage.
Now... let's get a little bit theoretical so that we make sure that we all see HOW the limiter is forced to be more or less 'savage' once the signal crosses the threshold of limiting, and into the realm of gain reduction.
Let's consider a nice, predictable, repetitive signal to which we want to apply some limiting. To keep things easily describable, we're going to consider a 'pulsing' sine-wave. -The frequency is not particularly important, but let's just say that it's 1kHz and be done with it.
Let's define the 'pulsing' so that we can all visualize the waveform. -This particular signal alternates between one level a 6dB louder level. Now if we input a 3 volt peak-to-peak sine wave, the PEAK level is 1.5Volts away from silence (1.5V up, 1.5V down) and doubles in the 'loud' bursts to 3V peak.
Now, let's say that our unit has a comparison threshold set JUST ABOVE the 'quiet' parts; at exactly 1.6 Volts. Even the very tallest parts of the quieter sections will sit just below the threoshold, but the (6dB boosted) LOUDER parts will cause the peaks of "the loud bits" to exceed the threshold by 1.4 Volts, (since they peak at 3V).
So -in this example- a 6dB 'surge' in a signal sitting just below the threshold produces 1.4V.
Now let's move BOOST the signal level using simple amplification. Let's double its size, so that the peaks of the quiet parts are now 3V from ground, and the peaks of the loud parts are now 6V from ground. We'll also raise the DC "comparison" threshold to 3.2 Volts.
In this second example, the quieter peaks (at 3.0V) do not cross the (3.2V) threshold, but now the SAME 'surge' in level (remember, the actual dB increase of the test signal has NOT been changed) produces peaks which -at 6.0V- exceed the threshold by 2.8V.
So... the same amount of volume change in the test signal (6dB both times, remember) produces MORE voltage at the output of the detector (which simply 'reports' when the signal exceeds the threshold voltage... and by how many volts) by a significantly larger amount.
Bearing that in mind for a moment, let's just make sure that we understand how the limiter controls he signal level. In simplest terms, we have a potential divider just like our 'ladder', formed right at the front end of the signal path. It's formed by R6 (where the signal from the unbalancing stage first comes in) and the FET Q1, which goes to ground. the 'tap' at the middle is where the 'sniffed' signal is passed on towards the output. If the FET Q1 has -for easy reckoning- a momentary value of 27k -which is exactly equal toR6- then the ongoing signal level is halved. Just like the earlier 'ladder' example, the signal level which is 'passed onwards' can be shown as the proportion of the FET's conduction resistance to the total resistance of the chain (R6 plus the FET).
So... we can REDUCE the signal level by shunting more of it to ground with the FET, but no matter what we do, we can never INCREASE it. -No matter HOW high the resistance of the FET, it can never exceed the total resistance of the 'chain', because the chain resistance is equal to the FET's resistance plus 27k.
Okay, so the amount of gain reduction is increased by an increasing voltage on the Fet's third terminal... -the Gate; the one with the arrow. In simple terms, more volts equals more gain reduction.
Since the same 'dB jump' in test signal level produces a greater amount of gain-reduction if we re-jig the signal gain and the 'voltage comparison' threshold, hopefully that helps show that the effective RATIO is therefore increased. (higher ratios produce greater gain reduction for the same increase in incoming signal level).
So, now that the THEORETICAL mechanism by which we want to change the effective ratio has been described, we can look back and -hopefully- see how the first ladder which we examined comes to play its role in the overall plan. -Already we've got preset GAIN CHANGE for each of our ratios. Now... to complete our functional ratio change, we need to alter the threshold point at which the detector reports that the signal is now crossing into 'gain change territory'.
So... looking back at our well-thumbed schematic, the circuit needs to be sensitive to both positive and negative going peaks, not just 'look at one peak and assume that the other half of the wave is the same'. -Human voice, strings, woodwind and brass instruments are all examples of HIGHLY asymmetric waveforms.
The detector ('gain reduction amplifier') does this by creating TWO outputs, in opposing polarity. One polarity output appears at the emitter of Q13. The inverted waveform appears at the emitter of Q15.
Now, if a peak appears at EITHER of these points which exceeds a comparison voltage, we want that 'amount' by which the waveform passes that threshold, and forward it to the gain reduction control point.
To do this for us, the two diodes (CR3 and CR4) take the AC-only parts of the waveforms coming from the two emitters, (the DC part being blocked by the two capacitors, C19 and C20), and ONLY pass any parts of the signal which exceed zero volts...since -being diodes- they don't conduct backwards.
Now of course, diodes would always conduct 'positive' voltages 'forward'... but taking a look at the circuit, point number 21 is 'dragged' NEGATIVE, via two resistors R74 and R75, which take a negative voltage from the wipers of another 'switched-resistor ladder' (the one which we haven't looked at yet), and use it to hold the diodes OUT of conduction until the 'high spots' of the signal get 'tall enough' to push the diodes ABOVE the zero volt line, at which point they will start to conduct, and the point where they join feeds the FET and starts to push it into gain reduction.
One or two small details I'd like to touch on: The time constant circuit (attack and release) is in between the 'output' of the diodes and the gate (voltage control input point) of the FET. -This makes sense, since it's where we "slow down" how quickly the FET reacts... -Simple enough, -yes? -the FINAL detail is that the voltage control doesn't ever go ALL THE WAY down to zero. -Right next to the time constant (attack/release) controls is one more adjustable resistance labeled "Q bias", which is there to hold the FET control voltage SLIGHTLY away from zero volts, so that it is always VERY slightly reducing the signal, even at "zero GR". This is a calibration thing, and is there to make sure that there's no 'dead spot' before the gain reduction starts... a bit like making sure that the clutch in a car is always 'slightly engaged' to ensure that the car moves IMMEDIATELY that the brakes are released... -Sorry, it's the best analogy I can think of right now. -If the clutch weren't slightly engaged, there'd be a 'hesitation' after the brakes are released and before drive begins... just like if the FET wasn't slightly biased into conduction, there'd be an analogous 'hesitation' between the detector starting to conduct and the FET starting to reduce gain... the 'gap' in the clutch in this analogy is what I'm trying to use to explain the FET's 'pinch-off' voltage, which varies slightly device-to-device and batch-to-batch.
So, if that explanation of HOW it is meant to work hasn't baffled everyone, in the next section I'll try to show what the effect of pressing multiple switches in might be, and why you shouldn't always put too much trust in gain reduction meters!